Test Engineer

Dale Wong
604 Harmony Lane
Pleasantville, CA 94588
(925) 555-1234


Electrical Engineer with experience in Computer Technology.


• VLSI Design • Control Engineering
• Digital Signal Processing • Digital Design
• Network Analysis • Random Signal & Noise
• Semiconductor Devices • Industrial Electronics
• TCP/IP • Computer Architecture
• Electrical Circuits • LAN


Zane Company, Fremont, CA
2000 - Present
Test Engineer
Responsible for PCB board-level functional testing, troubleshooting, and testing process and instruction configuration. Perform ICT test of DSL boards; burn-in test of Sun Microsystems motherboards; power module final diagnostic test of Intel CPUs; burn-in test of Xilinx BIOS; and test of high-end 3DFX graphic accelerators.

• Model SL120 Tadpole Cycle Computer motherboard based on Sun Microsystems architecture: 72-hour burn-in test with Sun Solaris 5 Operating System.• Acu Comm Internet Communications iDAC/iRacer/iModule Internet Router Simulation System with base and terminal: Data transmission length test to analyze failure signal.
• Quantum 3D AAlchemy 8164 High-end Graphic Accelerator, with 8 on-board 3DFX chip units: Xilinx BIOS burn-in test and PCB troubleshoot.
• Vina Tech E-Link 200/208/216 network product (Combines T1, Ethernet, and RS232): Data connection analysis between channels and IC controllers.
• Pycon PLB308 Power Module for Intel Pentium III/IV CPU core voltage test: Final diagnostic and voltage adjustment.
• Adastra ATX/ETX PCB Casino Data System motherboard and extension: Troubleshoot on-board BGA, AGP, and PCI interface.


International Technology University, Santa Clara, CA
MSEE, International Technology University, Santa Clara, CA
BSEE, National Taipei Institute of Technology, Taipei, Taiwan
In-Circuit Testing course with HP/Agilent 3070 Series II
Flying Probe Testing course with GenRad GR Pilot LX and GenRad's GR Alchemist III software suite


Avalanche Breakdown Voltages of Abrupt and Linearly Graded P-N Junctions.
- Performed general analysis of space charge, electric field, and potential distribution in Ge, Si, GaAs, and GaP.

Numerical Analysis for The Linearly Graded P-N Junction.
- Conducted fundamental analysis specified by Poisson's and time independent continuity equation.

Bipolar Transistor Model for Computer Simulation.
- Used Gummel-Poon model to obtain result of second-order effects on bipolar transistor characteristics in active mode.

TAP Controller State Machine using Verilog HDL.
- Wrote behavior model of TAP controller finite state machine, and created test bench to exercise all functions.

PRWRA Nick Marino - Outcome Resumes and Career Service - outcomerez@earthlink.net - Bishop, TX 78343